Facility Assignment And Design Line Generation Is Slow.
(Doc ID 1993903.1)
Last updated on MARCH 19, 2019
Applies to:
Oracle Communications MetaSolv Solution - Version 6.2.1 and laterInformation in this document applies to any platform.
Symptoms
Facility assignments and Design Line Generation is slow. When assigning T1 circuits to T3 or DS0 circuits to T1 the assignments take approximately 30 secs (in 6.2. version) where as in previous versions 6.0.16 /6.0.15 it were taking 10 secs .
Further ,the same type of Facility assignments are taking even more time approximately 50 secs to 2 mins to complete the assignments when T3 and T1 has open Order against them and we have a pending issue. Also when making a DS0 assignment to a T1 circuit individually it is taking 50 sects to 2 mins but when the same is done through group assignment process it is taking less than 5 secs.
This was impacting user and business productivity.
Changes
Cause
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In this Document
| Symptoms |
| Changes |
| Cause |
| Solution |
| References |