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Design Lines Are Scrambled Between Assignment Blocks On DLR (Doc ID 2092391.1)

Last updated on MARCH 14, 2019

Applies to:

Oracle Communications MetaSolv Solution - Version 6.2.1 and later
Information in this document applies to any platform.


When reconciling a circuit or attempting to move a block on the CLR/DLR Design page, the application will sometimes mix the lines from one block into another block existing on the design. The root cause was determined to be non-sequential ROW_SEQUENCE_NBR values on DLR_CIRCUIT_DESIGN_LINE that did not start with 1 for each design issue.


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