MSS 6.3.0 | Assignment Blocks Separated And interlaced/Scrambled On Design Lins/CLRs
(Doc ID 2636787.1)
Last updated on MAY 25, 2022
Applies to:
Oracle Communications MetaSolv Solution - Version 6.3.0 and laterInformation in this document applies to any platform.
Symptoms
MSS 6.3.0.940 Connection Design
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ACTUAL BEHAVIOUR
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Users are experiencing issues with shuffled assignments on CLR design lines. Causing users to do a great amount of rework.
Issues seen:
• Shuffling of assignment blocks, mixed up and out of sequence design lines, and duplicate assignment blocks.
• When trying to rearrange design lines and correct issue, users are noticing duplication of assignments and the design lines not updating properly.
• Multiple issue #s created for each design.
EXPECTED BEHAVIOUR
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When a user creates a design block or rearranges the design blocks , the blocks should NOT get interlaced/scrambled .
Steps :
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1-Working on the design of the circuits , like fac ,eqip assignment etc . Reconcile
Cause
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In this Document
| Symptoms |
| Cause |
| Solution |
| References |