MSS 6.3.0 | Assignment Blocks Separated And interlaced/Scrambled On Design Lins/CLRs
(Doc ID 2636787.1)
Last updated on FEBRUARY 12, 2020
Applies to:Oracle Communications MetaSolv Solution - Version 6.3.0 and later
Information in this document applies to any platform.
MSS 188.8.131.520 Connection Design
Users are experiencing issues with shuffled assignments on CLR design lines. Causing users to do a great amount of rework.
• Shuffling of assignment blocks, mixed up and out of sequence design lines, and duplicate assignment blocks.
• When trying to rearrange design lines and correct issue, users are noticing duplication of assignments and the design lines not updating properly.
• Multiple issue #s created for each design.
When a user creates a design block or rearranges the design blocks , the blocks should NOT get interlaced/scrambled .
1-Working on the design of the circuits , like fac ,eqip assignment etc . Reconcile
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