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MSS 630 | Background Processor Creates Overridden Design Issue On Top Of Pending Design Issue (Doc ID 2709166.1)

Last updated on MAY 25, 2022

Applies to:

Oracle Communications MetaSolv Solution - Version 6.3.0 and later
Information in this document applies to any platform.


On : 6.3.0 version, Other

Background processor creates overridden design issue on top of pending design issue which disables the user from performing any changes on the maximum issue.

If multiple modifications on the same equipment/equipment spec are performed in quick successions and all of these modifications are sent to the background processor, then the created jobs get executed parallel and creates overridden design issues on top of Pending issue on circuits assigned under the equipment.

Background processor should not create overridden design issue on top of pending design issues
after both the reconcile finishes.

1-Open the Equipment Inv of a location .
2-Locate a child circuit which is Getting Disconnected and have Pending circuit-issue.
3-Edit the equipment on which the circuit is present .Let the Reconcile be pushed to background-processor (BGP)
4-When the first reconcile is executing in the BGP, edit the equipment again and let the reconcile pushed to BGP. Soon we see 2 jobs executing in the BGP.
5-After the jobs are completed ,search the same circuit(as in step 2) in connection design and notice that it has the latest "Overridden" Issue.





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