Circuits Reconcile Problem While Adding Foreign Info To DLR (Doc ID 846247.1)

Last updated on SEPTEMBER 18, 2012

Applies to:

Oracle Communications MetaSolv Solution - Version 6.0.15 to 6.0.15 [Release 6.0.15]
Information in this document applies to any platform.

Symptoms


While adding Foreign Info on the Design ,  MSS is asking for a reconcile on one design while on the another design it is not.Both the circuits  have same number of child circuits. 

Cause

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