Circuits Moving To "PROBLEM" Status When Doing 'Assignment Cancel' In DLRD task.
(Doc ID 946552.1)
Last updated on DECEMBER 22, 2017
Applies to:Oracle Communications MetaSolv Solution - Version: 6.0.15
Information in this document applies to any platform.
When an order that has both parent and child circuits(eg: DS3, DS1,DS0 etc) on it, is supp cancelled, then during Assignment Cancel process, the circuits move to "PROBLEM" status in MSS.
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