Non-Cacheable Address Space tables for Sun[TM] Fire 3800/4800/4810/6800/E2900/E4900/E6900/V1280 and Netra[TM] 1280/1290 Server
(Doc ID 1006063.1)
Last updated on FEBRUARY 02, 2017
Applies to:Sun Fire E4900 Server - Version All Versions and later
Sun Fire 6800 Server - Version All Versions and later
Sun Netra 1280 Server - Version All Versions and later
Sun Netra 1290 Server - Version All Versions and later
Sun Fire E2900 Server - Version All Versions and later
This document provides tables of the Non-Cacheable Address Space for Sun Fire[TM] 3800-6800 systems. The tables can be used for decoding AFAR and (for USIII Cu) AFAR_2 registers on Sun Fire 3800-6800, v1280, and Netra[TM] 1280 systems. Decoding the registers in case of a Domain failure won't necessarily have anything to do with the error, but in practice it often helps to determine a suspect FRU(s).
Caution: This topic is quite complicated and it is recommended that customers needing to investigate this type of fault do so with caution. It's advisable to contact Support Services and open a Service Request for this to be resolved.
Refer to Document 1004877.1 for a cheatsheet that provides a breakdown of the address spaces listed in the tables below. The cheatsheet can be used to short circuit the manual decoding of address spaces with simple look-up tables for non-cacheable addresses.
- USIII: (CPU 750Mhz ) On USIII the AFAR register is supported. The AFAR is only valid if there is NO IERR/PERR Bit set.
- USIII Cu: (CPU >= 900Mhz) On a USIII Cu the AFAR and AFAR_2 are supported.
- PERR: If the Bit is set it indicates a Protocol Error.
- IERR: If the Bit is set it indicates an Internal Error.
- AFAR: Asynchronous Fault Address Register contains the physical address which caused the AFSR register to be set. If multiple errors occur the register is updated based on the priority of the errors. If the first error had a lower priority than the subsequent errors, it gets overwritten. Therefore, the AFAR register is not valid in all cases.
- AFAR_2: Asynchronous Fault Address Register 2/shadow, which always contains the physical address of the first error which caused the AFSR register to be set. If AFAR and AFAR_2 are different, the register for which the PERR Bit is set contains the first error and should be used for decoding.
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