SPARC M5-32 and M6-32 Servers: Processor numbering and decoding CPU location.
(Doc ID 1540202.1)
Last updated on JANUARY 03, 2019
Applies to:SPARC M6-32 - Version All Versions to All Versions [Release All Releases]
SPARC M5-32 - Version All Versions to All Versions [Release All Releases]
Information in this document applies to any platform.
Solaris[TM] device paths and messaging reference the ID of a given processor (in /var/adm/messages, console logs, core files, OBP probing, FMA logs etc.).
This document provides the cpuid cheat sheets for the SPARC M5-32 and M6-32 Servers.
By correctly mapping this ID to a physical location, we know that we are servicing the right component to resolve a hardware problem. An incorrect mapping could result in replacing and/or servicing the wrong component and could cause further outages or problems on the platform.
Also, on a sun4v architecture such as the M5-32 or M6-32 platform, this may help to understand how the cpus are assigned to the various domains.
When FMA indicts an component, the decoding is obviously automatically done and the indicted CMP or CMU is the one to be serviced.
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