Why are CPUs handling interrupts though they have been set to "no-intr" with psradm(1M)

(Doc ID 2155378.1)

Last updated on JUNE 29, 2016

Applies to:

Solaris SPARC Operating System - Version 11.3 and later
Information in this document applies to any platform.


After setting several CPUs to "no-intr" with psradm(1M) we can still see that the CPUs handle interrupts (e.g. in mpstat(1)). Why?


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