MSS 6.3.0 -Scrambled CLR/DLR Design Lines
(Doc ID 2633579.1)
Last updated on FEBRUARY 04, 2020
Applies to:
Oracle Communications MetaSolv Solution - Version 6.3.0 and laterInformation in this document applies to any platform.
Symptoms
MSS 6.3.0.982 Connection Design Lines
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ACTUAL BEHAVIOUR
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Muitple circuits showing in a scrambled CLR condition.
EXPECTED BEHAVIOUR
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The circuit design lines should not get scrambled .
Steps:
1-Open the Connection design of a circuit on which some design changes have been done .
2-We see scramabled design lines on it or on its child circuit's design.
This is not happening for all circuits but happening consistently for various types of circuits .
The work around is it remove the scrambled design block and add it back to the design.
Cause
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In this Document
| Symptoms |
| Cause |
| Solution |
| References |